Wafer grinding is used in the semiconductor industry for reducing the thickness during wafer fabrication. After the initial slicing from the ingot follows a series of steps to achieve the mirror like, low roughness surface required for device fabrication. One of these steps involves mechanical removal of the rough wire sawing profile and flattening of the surface, which can be done by lapping or grinding. A final polishing step (mechanical and/or chemical) follows to obtain a defect-free surface finish.
Because of the low cost (i.e. speed and the lack of polishing slurry required for processing) and the relatively low amount of damage induced, the grinding process has also been chosen to fulfill the requirements of thinning wafer/dies after the microelectronic devices fabrication for applications as smart cards and system stacking, e.g. memory for cell phones. Backside grinding after the microelectronic devices fabrication is largely used by the semiconductor industry to achieve die thicknesses that are moving down to 50 μm.
However, in this thickness range (<100 μm), the wafer becomes flexible and a carrier (e.g. Si or Glass wafer or a back grinding tape (BG-tape)) is used to provide mechanical support for the thin device wafer. The device wafer can be bonded to the carrier by means of a temporary glue layer (e.g. wax, resin or adhesive tape) or by using electrostatic force. Several products are available for this, depending on the requirements of the thinning process and following process steps. A problem with the use of a carrier and glue layer is that non-uniformities of the carrier or glue layer are transferred to the wafer during the thinning or grinding process, thereby increasing the total thickness variation (TTV) of the thinned device wafer.
Different techniques are used for wafer thinning, all having several drawbacks. U.S. 2006046433 describes the individual preparation of carriers for thinning semiconductor wafer by other methods such as lithography and etching. A disadvantage of this preparation of the carriers is that each individual carrier wafer must be adjusted to its particular device wafer.
WO9809804 describes a flattening process for bonded semiconductor substrates by selective etching (wet or dry) to reduce the thickness variation. A disadvantage of this flattening process is that each wafer must be analyzed and processed individually.
JP9117859 describes a polishing method for thinning quartz to very small thicknesses (<50 μm). However it also requires dedicated processing, i.e. spinning and lithography of a resist on the device wafer and underfilling of the gaps between the carrier wafer and device wafer with an adhesive. Even though very small TTV in the range of 0.1 μm can be achieved and 2 wafers can be processed simultaneously, there is a need for special machinery for performing this process (double side polisher) and a large amount of consumables (polishing slurry, photo resists, developers, etc).
Another major drawback for all the references presented above comes from the high cost of ownership of the thinning procedure due to the amount of machinery, consumables and time required to prepare each wafer stack before the thinning itself can be performed.